A technique of enhancing processor performance by using a DRAM having a greater capacity per unit area than an SRAM as a cache memory (L2 cache) is well known. In this technique, a CMOS chip and a DRAM chip are stacked, and tag data (such as address information and history) is stored in the CMOS chip.
On the other hand, recent processors employ a technique of reducing consumption of power by turning off power when idle state has continued for a predetermined period. In this case, if the supply of power to the CMOS chip and the DRAM chip is completely turned off, cache data and tag data will be lost, and further, the time required to re-load necessary data after re-switching on the circuit will become long.
To avoid the above, a process of not turning off the supply of power to the area of the CMOS chip storing the tag data or to the DRAM chip may be employed to protect the cache data and tag data. In this case, however, consumption of power will inevitably be increased.